1. Field of Invention
The present invention relates to a decoder, and more particularly to a decoder having a compact layout.
2. Description of Related Art
Various types of electronic devices have display devices, such as TVs, laptop computers, monitors and mobile communication terminals. The display devices are requested to be thin and light in order to save the volume and the cost of the electronic devices. To satisfy these requirements, various Flat Panel Displays (FPDs) have been developed as alternatives to the more conventional cathode ray tube displays.
A Liquid Crystal Display (LCD) is one kind of Flat Panel Display. The image data is input to a timing controller of the LCD, and then transmitted to a source driver. The source driver generates driving voltages corresponding to the image data for driving the LCD to display an image.
The color depth of a LCD is, for example, 6-bits (i.e. each of the Red, Green, Blue data have 6 bits), or 8-bits (i.e. each of the Red, Green, Blue data have 8 bits). The source driver should therefore have higher resolution if the color depth is higher.
However, increasing the resolution of a source driver increases cost. In particular, a digital-to-analog converter for converting input digital data to analog driving voltages is built in the source driver. Because the number of transistors included in a digital-to-analog converter (DAC) increases greatly according as the resolution increases, the higher resolution, the larger the DAC.
FIG. 1 shows a circuit diagram illustrating a conventional DAC. As illustrated in FIG. 1, the digital-to-analog converter 100 includes a full-type decoder 110 which receives 10-bit digital data to select one of gamma voltages based on the 10-bit digital data. The gamma voltages, which spread between the VA and the VS voltage levels, have total 1024 gamma voltages with 1024 voltage levels V0-V1023.
The decoder 110 receives 10-bit input digital data, i.e. bits D0, D1, D2, D3, D4, D5, D6, D7, D8, and D9, and inverted bits, i.e. D0B, D1B, D2B, D3B, D4B, D5B, D6B, D7B, D8B, and D9B, and the decoder 110 selects one gamma voltage among the gamma voltages V0, V1, V2, . . . , V1022, V1023 based on the 10-bit input digital data.
The decoder 110 includes 1024 transistor rows 111 respectively corresponding to gamma voltages V0, V1, V2 . . . V1022, and V1023. Each of the 1024 transistor rows 111 includes ten transistors connected in series, and each of the transistors receives one bit or inverted bit of the input digital data.
For example, while the input digital data are ‘0000000001’, the gamma voltage V1 will be output, because the gate of the corresponding transistor M10 is connected to D0, and the gates of the corresponding transistors M11-M19 are connected to the inverted signals D1B to D9B. The selected gamma voltage V1 is then output to the LCD.
However, a full-type decoder may occupy a very large chip area. For example, a 10-bit full-type decoder requires 1024 (i.e. 210) transistor rows 111, which have a large number (10×1024=10240) of transistors. Further, a 12-bit fall-type decoder requires 4096 transistor rows, which have 12×4096=49152 transistors, 4 times more than that of a 10-bit fall-type decoder.